Various voltage errors are associated with oerational amplifier circuits, including voltage errors resulting from parasitics capacitances associated with both nodal connections and the devices used to implement the circuits. A common parasitic-sensitive node of a differential amplifier is the input node which is selectively coupled directly to an output of the differential amplifier. A conventional method for compensating an offset voltage error associated with a differential amplifier is to periodically directly connect the output thereof to one of the inputs. Offset voltage compensation of this type automatically zeroes out offset voltage and such amplifier structures are commonly known as autozeroed operational amplifiers. However, due to parasitics associated with the switch used to implement the autozeroing and parasitics associated with the autozeroed node, a voltage error which is in addition to any offset voltage error is introduced at the input of the differential amplifier at the time of charge equalization between the input and output of the differential amplifier. Error voltages resulting from parasitic capacitance associated with electronic switches are well known as documented by Bing J. Sheu et al. in an article entitled, "Switch-Induced Error Voltage on a Switched Capacitor", in IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 4, August 1984, pp. 519-525. Others have attempted to compensate for parasitic related voltage errors by using an electronic switch which has additional compensation circuitry associated therewith to minimize parasitic related voltage errors. However, although such compensated switches substantially null parasitic errors created by the switch's internal parasitics, additional circuitry is required to implement the compensation while the number of devices connected to the input node has increased. As a result, the parasitic capacitance on the input node itself has been increased. Others who have used conventional CMOS swtiches have also attempted to adjust the width of the control electrodes of the transistors associated therewith so that P-channel device parasitics cancel N-channel device parasitics. However, exact matching of device characteristics is never acheivable due to processing variables.